The high frequency response of a representative state of the art heterojunction bipolar transistor, such as shown in FIG. 1 depends on the parasitic capacitances in a complex manner. The current gain cut-off frequency, f.sub.t, and the maximum frequency of operation, f.sub.max, are given by: ##EQU1## where g.sub.m is the transconductance, R.sub.B is the base resistance, C.pi. is the base-emitter capacitance, C.mu. is the base collector capacitance, R.sub.E is the emitter resistance and R.sub.C is the collector resistance. Equations (1) and (2) show that the high frequency response can be increased by either increasing the transconductance, g.sub.m, by reducing the resistances R.sub.B, R.sub.C, and R.sub.E or by reducing the capacitances C.pi. and C.mu.. Conventional manufacturing techniques using self-alignment technology are only effective in reducing the base resistance which increases the maximum frequency operation, f.sub.max, relative to the cut-off frequency, f.sub.t. Further, improvement of the cut-off frequency, f.sub.t, can be achieved by decreasing the dimensions of the heterojunction bipolar device so as to reduce the base emitter capacitance C.pi. and the base-collector capacitance, C.mu.. However, this reduction in the capacitances C.pi. and C.mu. is normally counteracted by increases in the collector and emitter resistances, R.sub.C and R.sub.E, respectively, resulting from the decreased dimensions. As the dimensions of the heterojunction bipolar transistor is reduced, the base-emitter capacitance, C.pi., decreases much faster than the base-collector capacitance, C.mu., because of the difference in the base and the collector regions. This implies that a fully self-aligned heterojunction bipolar transistor manufacturing process that reduces the base-collector capacitance C.mu., much more than the emitter resistance, R.sub.E, and collector resistance, R.sub.C, are increased, is needed to manufacture heterojunction bipolar transistors having high current gain cut-off frequencies, f.sub.t.
The prior art heterojunction bipolar transistor 10 shown in FIG. 1 has a semi-insulating semiconductor substrate such as a semi-insulating indium phosphide (InP) substrate 12 on which is grown an n.sup.+ indium gallium arsenide (InGaAs) subcollector layer 14. An n.sup.+ indium phosphide layer 16 forming a first mesa region. An n indium phosphide layer 18 is grown on top of n.sup.t indium phosphide layer 16 to form the collector and a p.sup.+ indium gallium arsenide base layer 20 is grown on top of the n indium phosphide layer 18 forming an intermediate mesa region. A top mesa region is formed by an n indium phosphide layer 22 as N.sup.+ indium phosphide layer 24 and n.sup.+ indium gallium aresenide emitter layer 26. Electrical contact to the subcollector layer 14, base layer 20 and emitter layer 26 by metallic contacts 28, 30 and 32, respectively, are made through a silicon oxide (SiO.sub.2) overlayer 34. As previously indicated, this heterojunction bipolar transistor structure has a relatively high extrinsic base-collector capacitance C.mu..
The invention is a method for making a heterojunction bipolar transistor in which the extrinsic base-collector capacitance is reduced by up to three orders of magnitude.